In an semiconductor device, such as a memory device including a flip-flop circuit, or a data latch circuit, if energetic particles, such as protons, neutrons or heavy ions, penetrate into a transistor as an element of the device, an electron-hole pair, i.e., excess opposite charges, is likely to be created in the element by the action of each energetic particle, such as ionization and excitation. The created electric charges are moved in opposite directions by an electric field in a reverse-biased PN junction region of the element (charge collection), and thereby the transistor in an OFF state is wrongly operated to temporarily have an ON state. Thus, a current which otherwise never occurs in a normal state will flow inside the semiconductor device to cause an error, such as inversion of data stored in the semiconductor device. This phenomenon is called “single-event upset” (SEU).
Such a malfunction due to penetration of energetic particles is also likely to occur in an external circuit connected to a clock signal input terminal or a data input terminal of a certain semiconductor device and cause an undesirable situation that the external circuit temporarily sends an abnormal clock signal or data signal to the semiconductor device. This current pulse which otherwise never occurs in a normal state is called “single-event transient current pulse”, and such a phenomenon is called “single-event transient (SET)”. The single-event transient current pulse applied to a semiconductor device is also likely to cause an error, such as inversion of data stored therein.
The phenomenon of occurrence of errors and defects in a semiconductor caused by incidence of energetic particles, such as the SEU and SET, is generally called “single-event effect (SEE)”. A typical single-event effect (SEE) includes the SET to be caused by direct penetration of energetic particles into a semiconductor device, and the SEU to be caused by propagation of an abnormal single-event transient current pulse to the semiconductor device. The SEE is often observed in high altitude, cosmic space and radiation-related facilities, which are circumstances having a high probability of the presence of energetic particles, and regarded as one obstructive factor to a normal operation of a computer under such environments. It is not a realistic approach to try to fully shield such energetic particles in a mechanical manner so as to prevent the SEE. In other words, as effective measures against the SEE, it is essentially required to achieve a memory device tolerant to the SEE by itself.
In advance of the following description, the definition of each code to be used in this specification will be shown as follows:                CK: input clock signal to be entered from outside;        CKi: clock signal to be generated internally (with the same phase as that of input clock signal CK);        CKB: input inverted clock signal to be entered from outside;        CKBi: inverted clock signal to be generated internally (with the same phase as that of input inverted clock signal CKB);        D: input data signal to be entered from outside;        G: input clock signal to be entered from outside;        Gi: clock signal to be generated internally (with the same phase as that of input clock signal G);        GBi: inverted clock signal to be generated internally        MO: intermediate output signal to be sent from master to slave within flip-flop circuit;        Q: output data signal to be sent to outside;        QB: inverted output data signal to be sent to outside;        XQ: inverted output data signal to be sent to outside;        VDD: source voltage from first voltage source; and        Vss: source voltage [0 (zero) V] from second voltage source.        
The clock signal is often used in such a manner as to be paired with the inverted clock signal generated by inverting the clock signal. This pair of the normal-phase and reversed-phase clock signal will be referred to as “complementary clock signals”. Two clock signals whose codes are different in only the presence or absence of the suffix “B” representing “reversed phase” are the pair of complementary clock signals.
[Conventional Data Latch Circuit]
The configuration and operation of a conventional data latch circuit will be described below. FIG. 2 is a circuit diagram showing a conventional data latch circuit 1, and FIG. 1 is a circuit diagram showing a clock generation circuit 1C1 for the conventional data latch circuit 1. The clock generation circuit 1C1 comprises an inverter 1I1 adapted to invert an input. The clock generation circuit 1C1 is operable, based on an input clock signal G entered from outside as a clock signal, to generate an inversed clock signal GBi having a polarity opposite to that of the input clock signal G. The generated inversed clock signal GBi is supplied to the data latch circuit 1 together with the input clock signal G The inverter 1I1 comprises a p-channel MOS transistor 1P1 and an n-channel MOS transistor 1N1 which are connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source (VDD) to a node connected to the side of a second voltage source (Vss).
In FIG. 2 which is a circuit diagram showing the conventional data latch circuit 1, a clocked inverter 1I3 and an inverter 1I4 makes up a storage node. An input data signal D is entered through a clocked inverter 1I2. The entered input data signal D is connected to the storage node.
As an output of the storage node, i.e., an output of the data latch circuit 1, an output of the clocked inverter 1I3 is sent out as an output data signal Q through a buffer circuit consisting of an inverter 1I5, and further an output of the inverter 1I4 is sent out as an output data signal XQ through a buffer circuit consisting of an inverter 1I6.
The clock generation circuit 1I1 illustrated in FIG. 1 is used in combination with the data latch circuit 1 to generate an inverted clock signal GBi to be entered into the data latch circuit 1. In the data latch circuit 1, when an input clock signal G is at a low level, an output data signal Q is sent out at the same logic level as that of an input data signal D (through mode or transparent mode). At a rise timing of an input clock signal G, an input data signal D is loaded from the clocked inverter 1I2 serving as an input stage of the data latch circuit 1, and latched. The latched data will be held during a period where the input clock signal G is at a high level (latch mode). Specifically, the latched data is held by the storage node consisting of the clocked inverter 1I3 and the inverter 1I4 which are cross-connected between respective outputs and inputs thereof. Then, the latched data will be sent out as an output data signal Q and an inverted output data signal XQ, respectively, from the inverter 1I5 and the inverter 1I6 each serving as a buffer circuit.
Now, the SEE will be discussed. As one example, given that a transistor of either one of the clocked inverter 1I3 and the inverter 1I4 which make up a storage node is changed from an OFF state to an ON state during the latch mode due to penetration of energetic particles. Thus, an output of the inverter including the affected transistor is shifted to an opposite logic level, and this change in logic value is entered into the other inverter to invert its output. Consequently, a logic value in the storage node is inverted to cause the SEU.
During the latch mode, the input-stage clocked inverter 1I2 as the input stage is kept in an OFF state to prevent an input data signal D from being transferred to a subsequent stage, and the storage-node clocked inverter 1I3 is kept in an ON state to store/hold a certain logic state. However, if a SET-induced voltage change which allows the input-stage clocked inverter 1I2 to be changed from the OFF state to the ON state is entered from an upstream, the input data signal D will be (inversed and) sent to the subsequent stage, and the storage-node clocked inverter 1I3 is changed to the OFF state to allow inversion of the logic state. In this timing, if the input data signal D has a logic level opposite to the logic state stored in the storage node, the stored data will be inverted to cause the SEE. As above, the conventional data latch circuit is extremely vulnerable to the SEE.
[Conventional Flip-Flop Circuit]
The configuration and operation of a conventional flip-flop circuit will be described below. FIG. 4 is a circuit diagram showing a conventional flip-flop circuit 2, and FIG. 3 is a circuit diagram showing a clock generation circuit 2C1 for the conventional flip-flop circuit 2. This flip-flop circuit 2 is a master-slave type D flip-flop. A clocked inverter 2I4 and an inverter 2I5 make up a pre-stage storage node, and a clocked inverter 2I6 and an inverter 2I7 make up a post-stage storage node. An input data signal D is entered through an inverter 2I3 serving as a buffer circuit. The entered input data signal D is connected to the pre-storage node via a transmission gate 2S1. The pre-stage storage node has an output connected to the post-stage storage node via a transmission gate 2S2. As an output of the post-stage storage node, i.e., an output of the flip-flop circuit 2, an output of the clocked inverter 2I6 is sent out as an inverted output data signal XQ through a buffer circuit consisting of an inverter 2I8 and an inverter 2I9, and further an output of the inverter 2I7 is sent out as an output data signal Q through a buffer circuit consisting of an inverter 2I10 and an inverter 2I11.
The clock generation circuit 2C1 illustrated in FIG. 3 is used in combination with the flip-flop circuit 2 to generate a clock signal CKi and an inversed clock signal CKBi. In the flip-flop circuit 2, when an input clock signal CK is at a low level, the clock signal CKi and the inversed clock signal CKBi are, respectively, at a low level and at a high level, and an input data signal D is loaded through the transmission gate 2S1 in an ON state. At the same time, the transmission gate 2S2 is in an OFF state, and thereby the input data signal D is not transferred from the transmission gate 2S2 to a subsequent stage. In this state, if the input clock signal CK is changed from the low level to a high level, the transmission gate 2S1 will be changed to an OFF state to preclude the input data signal D from being loaded into the flip-flop circuit 2. However, a logic state just before the change of the clock signal CKi to the high level is stored in the pre-stage storage node (master) consisting of the clocked inverter 2I4 and the inverter 2I5, and this stored logic state is transferred to the post-stage storage node (slave) via the transmission gate 2S2 which is changed to an ON state. In this timing, the clocked inverter 2I6 is in an OFF state, and thereby the post-stage slave does not store/hold the logic level in the storage node thereof. Therefore, the output transferred from the pre-stage master is sent out as an inverted output data signal XQ through the buffer circuit consisting of the inverter 2I8 and the inverter 2I9. Further, the output transferred from the pre-stage master is inverted by the inverter 2I7, and then sent out as an output data signal Q through the buffer circuit consisting of the inverter 2I10 and the inverter 2I11. Then, if the input clock signal CK is changed from the high level to the low level, the transmission gate 2S2 will be changed to the OFF state to preclude an output of the post-stage master from being transferred to the post-stage slave. At the same time, the clocked inverter 2I6 of the post-stage slave is changed to an ON state, and thereby the post-stage slave stores/holds a logic level just before the event. Thus, both the output data signal Q and the inverted output data signal XQ will be continuously sent out at the logic level just before the clock signal CKi is changed to a low level.
Now, the SEE will be discussed. As one example, given that, when the input clock signal CK is at the low level, and the post-stage slave of the flip-flop circuit 2 holds a certain logic level, a transistor of either one of the clocked inverter 2I6 and the inverter 2I7 which make up the post-stage storage node is changed from an OFF state to an ON state due to penetration of energetic particles.
Thus, an output of the inverter including the affected transistor is shifted to an opposite logic level, and this change in logic value is entered into the other inverter to invert its output. Consequently, a logic value in the storage node is inverted to cause the SEU.
In a state when the input clock signal CK is at the high level, the transmission gate 2S1 is kept in the OFF state to prevent an input data signal D from being transferred/entered to/into the pre-stage master, and the clocked inverter 2I4 of the pre-stage master is kept in an ON state to store/hold a certain logic state. However, if a SET-induced voltage change which allows the transmission gate 2S1 to be changed from the OFF state to an ON state is entered from an upstream, the input data signal D will be (inversed and) sent to the subsequent stage, and the clocked inverter 2I4 of the pre-stage master is changed to an OFF state to allow inversion of the logic state. In this timing, if the input data signal D has a logic level opposite to the logic state stored in the pre-stage storage node, the stored data will be inverted to cause the SEE. As above, the conventional flip-flop circuit is extremely vulnerable to the SEE.
[Conventional Single-Event Effect (SEE) Tolerant Device]
Heretofore, there has been known the following memory device with a configuration tolerant to the SEE (see, for example, the following Patent Publication 1). FIG. 6 is a circuit diagram showing a conventional SEE-tolerant data latch circuit 3. This data latch circuit 3 is also called “DICE (Dual Interlocked Storage Cell)”. FIG. 5 is a circuit diagram showing a clock generation circuit 3C1 for the conventional data latch circuit 3. With reference to FIG. 6, the configuration of the data latch circuit 3 will be described below.
The data latch circuit 3 is a single-event upset (SEU) tolerant (hardened) latch circuit which generally comprises: a first dual-port inverter (3IP1) for receiving a first input (D), wherein the first input is coupled to the first dual-port inverter via a first set of pass gates (3S1 and 3S3); and a second dual-port inverter (3IP2) coupled to the first dual-port inverter (3IP1) via a second set of pass gates (3S2 and 3S4); and an output node connected to the first dual-port inverter (3IP1) and the second dual-port inverter (3IP2). In this data latch circuit 3, the coupling between the first dual-port inverter (31P1) and the second dual-port inverter (3IP2) is established by allowing an output of the second dual-port inverter (3IP2) to be coupled to the first dual-port inverter (3IP1) via the second set of pass gates (3S2 and 3S4).
The first dual-port inverter (3IP1) has the following configuration. The first dual-port inverter (3IP1) includes a first inverter (3I4) and a second inverter (3I6). The first inverter (3I4) includes a first transistor (3P6) connected in series to a second transistor (3N6), and the second inverter (3I6) includes a third transistor (3P10) connected in series to a fourth transistor (3N10). A gate of the first transistor (3P6) is connected to a gate of the fourth transistor (3N10) to provide a first inverter input node. A gate of the second transistor (3N6) is connected to a gate of the third transistor (3P10) to provide a second inverter input node. Further, the first and second transistors (3P6, 3N6) provide a first inverter output node, and the third and fourth transistors (3P10, 3N10) provide a second inverter output node. The first and second inverters (3I4, 3I6) are adapted to receive identical inputs to provide a valid output at either the first inverter output node or the second inverter output node. In this data latch circuit 3, as a first inverter output, an inverted output QB is provided to the first inverter output node. Each of the first and third transistors (3P6, 3P10) is a p-channel transistor, and each of the second and fourth transistors (3N6, 3N10) is an n-channel transistor.
The second dual-port inverter (3IP2) has the following configuration. The second dual-port inverter (3IP2) includes a first inverter (3I3) and a second inverter (3I5). The first inverter (3I3) includes a first transistor (3P3) connected in series to a second transistor (3N3), and the second inverter (3I5) includes a third transistor (3P7) connected in series to a fourth transistor (3N7). A gate of the first transistor (3P3) is connected to a gate of the fourth transistor (3N7) to provide a first inverter input node. A gate of the second transistor (3N3) is connected to a gate of the third transistor (3P7) to provide a second inverter input node. Further, the first and second transistors (3P3, 3N3) provide a first inverter output node, and the third and fourth transistors (3P7, 3N7) provide a second inverter output node. The first and second inverters (3I3, 3I5) are adapted to receive identical inputs to provide a valid at either the first inverter output node or the second inverter output node. Each of the first and third transistors (3P3, 3P7) is a p-channel transistor, and each of the second and fourth transistors (3N3, 3N7) is an n-channel transistor.
The data latch circuit 3 is adapted to suppress the SEE to some extent according to the following operations. As one example, given that the data latch circuit 3 is in a latch mode where an input clock signal CK is at a low level and an inversed clock signal is at a high level, wherein an input data signal D just before shift to the latch mode is at a low level, and this input data signal D is latched. In this state, an input and an output of the first dual-port inverter 31P1 (inverter 3I4, inverter 3I6) are at a low level and at a high level, respectively. Further, an input and an output of the second dual-port inverter 3IP2 (inverter 3I3, inverter 3I5) are at a high level and at a low level, respectively. The SEE will occur when one of the transistors is changed from an OFF state to an ON state. In this example, given that the transistor 3N6 is changed from an OFF state to an ON state, and the output of the inverter 3I4 is temporarily changed to a low level. Further, given that, when both the transistors in each of the remaining inverters are in an ON state, a logic level of the output thereof is reversed in the same manner. The low level of the output from the inverter 3I4 is entered into the inverter 3I3 (transistor 3N3 includes therein) and the inverter 3I5 (transistor 3P7 includes therein). As to the inverter 3I3, the transistor 3N3 is changed from the ON state to an OFF state, and thereby all of the transistors in the inverter 3I3 have their OFF state. Thus, while the output node of the inverter 3I3 will have a high impedance state over time, the logic level just before the event can be maintained to some extent without being inversed. In this manner, the inverter 3I3 blocks from exerting influences of the SEE on a subsequent stage. As to the inverter 3I5, the transistor 3P7 is changed from the OFF state to an ON state, and thereby the output of the inverter 3I5 is reversed to have a high level.
After passing through the pass gate 3S4, the high level of the output from the inverter 3I5 is entered into the inverter 3I6 (transistor 3P10 includes therein) and the inverter 3I4 (transistor 3N6 includes therein). As to the inverter 3I6, the transistor 3P10 is changed from the ON state to an OFF state, and thereby all of the transistors in the inverter 3I6 have an OFF state. Thus, while the output node of the inverter 3I6 will have a high impedance state over time, the logic level just before the event can be maintained to some extent without being inversed. In this manner, the inverter 3I6 blocks from exerting influences of the SEE on a subsequent stage. As to the inverter 3I4, the input to the transistor 3N6 is inversed from a low level to a high level to exert an action of turning on the transistor 3N6. This action becomes a negative factor causing a worse situation than the initially assumed SEE. However, as mentioned above, there is the inverter, such as the inverter 3I3 and the inverter 3I6, where both the transistors thereof are turned off to allow the output node of the inverter to have a high impedance state so as to prevent influences of the SEE from being exerted on the subsequent stage. Thus, after termination of the SEE, the inverters will return to their original states. In this manner, even if either one of the transistors malfunctions, i.e., has an error, the SEE becomes unlikely to occur in the data latch circuit 3 in its entirety.
However, as the result of various experimental tests, it has been revealed that the SEE tolerance of the conventional data latch circuit 3 is not exactly sufficient. For example, when two or more of the transistors simultaneously malfunctioned due to penetration of energetic particles, the logical state of the storage node was inversed in some tests. Further, when a clock signal from the upstream was inversed due to the SET, the data latch circuit 3 in the latch mode was changed to the through mode to load an input data signal, and thereby stored data was inversed in some tests. As above, the reversion of an output due to the SEE was observed even in the data latch circuit 3 taking measures against the SEE. In view of significantly harmful effects of the SEE, it is desirable to maximize the tolerance to the SEE. Thus, there is the need for providing a semiconductor device, such as a memory device or a data latch circuit, with further enhanced SEE tolerance.
[Patent Publication 1] U.S. Pat. No. 6,327,176